The breakdown voltage and the operating resistance (On resistance or Rdson) are important characteristics of a power semiconductor device. The Rdson and the breakdown voltage of a power semiconductor device are inversely related. That is, the improvement in one adversely affects the other. To overcome this problem, U.S. Pat. No. 5,998,833 proposes a trench type power semiconductor in which buried electrodes are disposed within the same trench as the gate electrodes in order to deplete the common conduction region under reverse voltage conditions, whereby the breakdown voltage of the device is improved. As a result, the resistivity of the common conduction region can be improved without an adverse affect on the breakdown voltage.
Referring to FIG. 1, a power semiconductor device according to the disclosure of PCT/US2005/022917, assigned to the assignee of the present application, is a trench type MOSFET, which in the active area thereof includes trench 10 in semiconductor body 56. Trench 10 extends from the top 14 of semiconductor body 56 through source regions 16, and base region 18 into drift region 20.
A device according to FIG. 1 includes: first gate electrode 22 adjacent one sidewall of trench 10 and spanning base region 18; second gate electrode 24 adjacent the opposing sidewall of trench 10 and spanning base region 18; first gate insulation 26 interposed between base region 18 and first gate electrode 22; second gate insulation 28 interposed between second gate electrode 24 and base region 18; and source field electrode 30 having a first portion disposed between first and second gate electrodes 22, 24 and a second portion disposed below first and second gate electrodes 22, 24. First gate electrode 22 and second gate electrode 24 are electrically connected to one another so that they may be activated together, but are insulated from source field electrode 30. Specifically, the first portion of source field electrode 30 is insulated from first and second gate electrodes 22, 24 by respective insulation bodies 32, and insulated from drift region 20 by bottom insulation body 34, which is preferably thicker than first and second gate insulations 26, 28. Preferably, bottom insulation body 34 extends underneath first and second gate electrodes 22, 24.
The device further includes source contact 36 which is electrically connected to source regions 16, source field electrode 30, and high conductivity contact regions 38 in base region 18. To insulate gate electrodes 24, 26 from source contact 36, first insulation cap 40 is interposed between source contact 36 and first gate electrode 22, and second insulation cap 42 is interposed between source contact 36 and second gate electrode 24. Thus, the device according to FIG. 1 includes two insulated gate electrodes, and a source field electrode which is electrically connected to the source contact and disposed between the two gate electrodes and extends to a position below the gate electrodes.
Semiconductor body 56 is preferably comprised of silicon, which is epitaxially formed over a semiconductor substrate 58, such as a silicon substrate. The device further includes drain contact 43, which is in ohmic contact with substrate 58, whereby vertical conduction between source contact 36 and drain contact 43 is made possible.
A device according to FIG. 1 can have a drift region with an increased doping concentration compared to a standard trench MOSFET of the same voltage rating. It has been observed that in a device according to FIG. 1 the depleted region extends significantly into the channel region, which creates a large region of overlap between the gate oxide and the drain, leading to high Qgd, even though the bottom of the gate poly is planar with the pn-junction.
There are several known methods to reduce Qgd.                1. For example, increasing the gate oxide thickness can reduce Qgd. The gate oxide thickness, however, also determines the device threshold voltage, and a thicker oxide will result in higher on-resistance.        2. To reduce Qgd the gate oxide to drift region (drain) overlap can be reduced based on the zero-bias pn junction depth. However, once the bottom of the gate is above the pn junction the device on-resistance will increase. It is also difficult to control the absolute trench depth.        3. The concentration of dopants in the drift region can be reduced to reduce Qgd, which would increase the device on-resistance significantly.        